I2C Master IP

A memory-mapped I2C master that lets any AXI4-Lite master drive a two-wire bus through twelve 32-bit registers. Bit timing, framing, acknowledge handling, clock-stretch recovery and multi-master arbitration are all handled in hardware software queues transactions and reads a status word.

Overview

The RunX I2C Master Controller bridges an AMBA AXI4-Lite register interface to a standard two-wire I2C bus. It implements START, repeated-START and STOP framing, 7-bit addressing, byte-level acknowledge, slave clock-stretching with a programmable timeout, and multi-master arbitration-loss detection. Bit timing is elaborated from the SYS_CLK and I2C_CLK parameters, so there is no runtime clock-divider to program and no chance of a mismatch between the bitstream and the driver. A 32-word transmit and a 32-word receive FIFO decouple software from the bus: a driver can queue a whole batch of transactions, set one bit, and service a single completion.

Specifications

Specification	Value
Bus interface	AMBA AXI4-Lite, 8-bit address, 32-bit data
Bit rates	Standard 100 kHz, Fast 400 kHz (100 kHz – 800 kHz)
Addressing	7-bit, with read/write direction bit
Payload	0 – 4 bytes per transaction, up to 255 transactions per batch
FIFO depth	32 words × 32 bits, TX and RX (parameterisable)
FIFO storage	Block RAM · distributed RAM · registers
Registers	12 × 32-bit, offsets 0x00 – 0x2C
Interrupt	One level-sensitive line, compare-match on received data
Clock domains	1 synchronous (s_axi_aclk) + the asynchronous I2C bus
Source language	SystemVerilog, with a Verilog-2001 wrapper for packagers
Vendor support	AMD Xilinx · Altera · Microchip · Lattice
Logic (preliminary)	≈ 400 LUT / 375 FF · 2 × RAMB18 · 0 DSP
Fmax	Characterization pending
Resource figures are post-synthesis on a Kintex-7 xc7k70tfbv676-1 in Vivado
2025.2, at the default parameter set. They are preliminary and subject to
per-device characterization.

AXI4-Lite transaction

A register write is a single-beat AXI4-Lite transaction; the slave converts an accepted write into one backend pulse carrying address, data and byte strobes.

How it compares

	RunX I2C Master	AMD/Xilinx AXI IIC	Altera i2c_master
Resource usage	~ 388 LUT / 375 FF / 2 BRAM	375 LUT / 356 FF	347 ALM / 483 FF
Fmax	256 MHz	280 MHz	346 MHz
Software controllable	12 registers + bare-metal C driver	bare-metal C driver	bare-metal C driver
AXI support	AXI4-Lite slave, native	AXI4-Lite slave, native	not native
Custom frequency	Any SYS_CLK / I2C_CLK pair, set at elaboration	Any SYS_CLK / I2C_CLK pair, set at elaboration	Any SYS_CLK 100/400 KHz I2C_CLK pair, set at runtime!

Other columns are to be completed from the current vendor datasheets & implementations.. Resource and frequency figures are only comparable when measured on the same device family and speed grade, so each cell should record the part it was taken on.

Parameterisation

Every parameter is resolved at elaboration, so nothing has to be programmed at run time and nothing can drift between the bitstream and the driver.

Parameter	Purpose
SYS_CLK	System clock frequency, 1 MHz – 250 MHz
I2C_CLK	Target bit rate, 100 kHz – 800 kHz
FIFO_DEPTH	Depth of both FIFOs, in 32-bit words
FIFO_MEM_TYPE	block · distributed · REG
DEVICE	Vendor inference hint: Xilinx · Altera · Lattice · Microchip · generic
VERSION / BUILD_DATE	Values returned by the read-only ID registers

Verification

The core ships with its verification environment, not just its RTL. A UVM verification IP provides master and slave agents, protocol checkers for START/STOP framing and acknowledge behaviour, a scoreboard and functional coverage across addressing modes, byte counts, clock-stretch and arbitration scenarios.

Aspect	Detail
Environment	UVM agents, protocol checkers, scoreboard, functional coverage
Simulators	Vivado xsim · Questa / ModelSim
Delivered scripts	Testbench and regression runners for both simulators
Scenario coverage	Addressing, byte count, clock stretching, arbitration loss, NACK
Current status	Regression pending against the latest RTL revision

Deliverables

• ✓ Synthesizable SystemVerilog RTL source
• ✓ Verilog-2001 transparent wrapper for IP packagers and encryption flows
• ✓ Bare-metal C driver and register header
• ✓ Timing constraint
• ✓ Simulation run scripts for xsim and Questa
• ✓ UVM verification IP (licensed separately)
• ✓ Product User Guide (PDF)
• ✓ Block diagrams and WaveDrom timing sources

Why this core ?

Verification. The differentiator is that the verification environment is a product, not an afterthought a UVM VIP with protocol checkers and coverage, delivered alongside the RTL and runnable in two simulators. Multi-vendor by construction. The RTL instantiates no vendor primitive. The same source targets AMD Xilinx, Altera, Microchip and Lattice; DEVICE changes inference hints only, so there is no vendor-specific fork to maintain. Parameterisation. Clock ratio, FIFO depth, FIFO storage style, device target and identification registers are all elaboration-time parameters. The bit rate is derived, not programmed, so a build cannot be mis-configured at run time. Software included. A bare-metal C driver with a documented API ships with the core, so bring-up is a function call rather than a register-level integration exercise.

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