SPI Flash Controller
Most SPI flash controllers commit you to one FPGA vendor and one flash part before you write a line of driver code. The RunX SPI Flash Controller is built the other way around: a single synthesisable SystemVerilog core, proven across four independent FPGA toolchains, drives serial NOR, NAND, EEPROM and FRAM devices over a standard, dual or quad SPI link from an AXI4-Lite register interface. Its command engine is opcode-agnostic — a driver describes a flash command as a short list of phase-typed segments (opcode, address, dummy, data) and the engine walks that list, so retargeting to a different vendor’s device is a register-configuration exercise, not an RTL change. This brief summarises the core; the Datasheet and User Guide are the full specification.
Features
• One RTL, four independent FPGA toolchains — no vendor lock-in, zero vendor primitives
• Silicon-proven on real hardware, zero errors against a genuine flash device
• Opcode-agnostic command engine drives any SPI NOR, NAND, EEPROM or FRAM device — no per-part redesign
• Hardware automates write-enable and status polling, so firmware never blocks on a busy loop
• Standard, dual and quad SPI lane modes from one parameterised core
• Optional memory-mapped XIP window — read, plus optional buffered write (PROGRAM) with a hardware write floor, detectable at run time
• Full AXI4-Lite integration — control plane and optional XIP window
• SFDP (JESD216) self-discovery built in, no per-device driver rewrite
• 264-byte transmit/receive FIFOs and six maskable interrupt sources
• Single clock domain — no CDC risk
1.1 Overview
RunX SPI Flash Controller bridges an AXI4-Lite register interface to a serial NOR flash, NAND flash, EEPROM or FRAM device over standard, dual or quad SPI. It implements segment-based command framing, chip-select hold across segment boundaries, hardware auto write-enable and auto status polling, and presents the bus to software as a small fixed register file plus a pair of FIFOs.
The core is delivered as five cooperating modules behind a single top level: an AXI4-Lite register file (axil_regs), a segment walker (seg_engine) that owns phase decode and chip-select, an orchestration layer (seq_orchestrator) for auto write-enable/poll, a vendor pin adapter (phy_wrap), and an optional memory-mapped window (xip_window) that serves reads and, when built with XIP_WRITE_ENABLE, buffered page-program writes. A transparent Verilog delivery wrapper, IP_spi_flash_controller.v, carries the interface through to device pins.
1.2 Key Features
• Vendor-agnostic RTL, proven across four independent FPGA toolchains, no vendor primitive anywhere
• Segment-based command engine: OPCODE / ADDRESS / DUMMY / DATA phases, no opcode literal in the datapath
• AXI4-Lite slave, full write and read channels, per-byte write strobes, SLVERR on unmapped/unaligned offsets
• Standard, dual and quad SPI lanes, elaborated from a single LANE_MODE parameter
• SPI clock is a programmable divide of the system clock (CLKDIV, minimum divide-by-4), 30 MHz SPI clock silicon-validated at 120 MHz system clock
• Hardware auto write-enable and auto status polling, with configurable opcode, bit position and polarity
• Optional XIP read window on a second AXI4-Lite slave
• Optional XIP write (XIP_WRITE_ENABLE): writes to the same window are buffered into a 256-byte page and sent as a PROGRAM job, write-enable, page program and busy polling in hardware, after a configurable number of writes or on an explicit flush; PROGRAM only (never erase), with a hardware write floor (XIPWFLOOR) that refuses writes below a programmable address without any SPI activity
• 264-byte transmit/receive FIFOs (parameterisable) and six maskable interrupt sources
• SFDP (JESD216) discovery sequence and parsing offsets provided in the driver header
1.3 Target Applications
• Bulk non-volatile storage and data logging for embedded and industrial designs
• FPGA/SoC configuration and golden-image storage on the same flash the device boots from
• Firmware or asset storage behind a simple, non-cached memory-mapped read window (XIP), with optional in-place update of pre-erased flash through the write window
• Multi-vendor flash retargeting via SFDP discovery instead of a per-part driver rewrite
• Designs needing verified single-, dual- and quad-lane operation from one parameterised core
1.4 Portability
RunX SPI Flash Controller is delivered as a vendor-agnostic soft IP core: synthesisable SystemVerilog RTL with no vendor-specific primitives, tested on Xilinx, Altera, Lattice and Microchip vendors.
1.5 Maximum Frequency Table
The maximum frequency table is available in the Product Brief.
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