UART Controller IP

A memory-mapped UART that lets any AXI4-Lite master send and receive asynchronous serial data through four 32-bit registers. Bit timing, framing, parity, oversampled receive sampling and error detection are all handled in hardware software pushes and pops whole bytes.

Overview

The RunX UART Controller bridges an AMBA AXI4-Lite register interface to a full-duplex asynchronous serial link. All bit-level timing is elaborated at build time from the G_CLK_FREQ_HZ and G_BAUD_RATE parameters, so there is no runtime baud-rate register and no chance of a mismatch between the bitstream and the driver.

Independent transmit and receive FIFOs decouple software from the line rate, and the receiver hardens the link with a three-sample majority vote centred on every bit, so isolated noise on the line does not corrupt a frame. A single maskable, level-sensitive interrupt reports both “TX space available” and “RX data ready”.

Specifications

Specification	Value
Bus interface	AMBA AXI4-Lite, 4-bit address, 32-bit data
Framing	5 – 8 data bits · None/Even/Odd parity · 1 – 2 stop bits
Baud rate	Any (elaborated from `G_CLK_FREQ_HZ` / `G_BAUD_RATE`)
Oversampling	3-sample majority vote per bit
FIFO depth	Power of two (parameterisable), independent TX and RX
Registers	4 × 32-bit, offsets 0x00 – 0x0C
Interrupt	One level-sensitive line, TX-space / RX-data / error
Clock domains	1 synchronous (`s_axi_aclk`) + the asynchronous RX line
Source language	VHDL, with a Verilog-2001 wrapper (`IP_uart.v`) for packagers
Vendor support	AMD Xilinx · Altera · Lattice · Microchip
Logic ( Altera, Agilex 3)	203 LUT / 211 registers · 256 b mem · 0 DSP
F_max ( Altera)	440.1 MHz

Altera figures are real Quartus Prime synthesis results. AMD/Xilinx logic is ≈150–200 LUT / ≈193 registers on a Kintex-7 reference build; Xilinx F_max is not yet established the reference timing run did not constrain a clock path, so no number is quoted rather than an unverified one.

How it compares

	RunX UART	AMD/Xilinx AXI UART Lite
Resource usage	203 LUT / 211 FF	89 LUT / 110 FF
Fmax	440.1 MHz (Altera)	416 MHz
Software controllable	4 registers + bare-metal C driver	bare-metal C driver
AXI support	AXI4-Lite slave, native	AXI4-Lite slave, native
RX noise immunity	3-sample majority vote per bit	No oversampling

Other columns are to be completed from the current vendor datasheets & implementations.. Resource and frequency figures are only comparable when measured on the same device family and speed grade, so each cell should record the part it was taken on.

Parameterisation

Every parameter is resolved at elaboration, so nothing has to be programmed at run time and nothing can drift between the bitstream and the driver.

Parameter	Purpose
`G_CLK_FREQ_HZ`	System clock frequency the baud generator is built for
`G_BAUD_RATE`	Target baud rate, elaborated against `G_CLK_FREQ_HZ`
`G_DATA_BITS`	Data bits per frame, 5 – 8
`G_PARITY`	`NONE` · `EVEN` · `ODD`
`G_STOP_BITS`	Stop bits per frame, 1 – 2
`G_FIFO_DEPTH`	Depth of both FIFOs, power of two
`G_DEVICE`	Vendor inference hint: Xilinx · Altera · Lattice · Microchip · generic

Verification

Aspect	Detail
Environment	Self-checking VHDL testbenches (`tb_uart_full`, `tb_uart_master_top`, `tb_uart_verif`)
Co-simulation	C/RTL driver co-simulation through a DPI bridge
Scenario coverage	Byte loopback across frame formats, FIFO overflow/underflow, sticky-error assertion and clearing, TX/RX interrupt conditions
Current status	Directed simulation passing; a constrained-random UVM environment is planned as a separate Verification IP deliverable

Deliverables

✓ Synthesizable VHDL RTL source
✓ Verilog-2001 transparent wrapper (IP_uart.v) for IP packagers
✓ Bare-metal C driver and register header
✓ Timing constraint
✓ Self-checking testbenches and simulation scripts
✓ Product User Guide (PDF)
✓ Block diagram source

Why this core

Baud rate can’t drift. The bit rate is elaborated from G_CLK_FREQ_HZ and G_BAUD_RATE at build time, not programmed at run time a bitstream and its driver can never disagree about the line rate.

Multi-vendor by construction. The RTL instantiates no vendor primitive. The same source targets AMD Xilinx, Altera, Lattice and Microchip; G_DEVICE changes inference hints only.

Noise-hardened receive path. A 3-sample majority vote at every bit centre, plus independent framing and parity checks, catches the kind of isolated line noise a naive single-sample UART misses.

Software included. A bare-metal C driver with blocking, timeout and non-blocking transfer paths ships with the core, so bring-up is a function call rather than a register-level integration exercise.

FEATURES LIST

Full AXI4-Lite slave

▶ Compliant AW/W/B/AR/R handshaking, OKAY responses and byte strobes honoured on every writable register.

Configurable framing

▶ 5 to 8 data bits, NONE/EVEN/ODD parity and 1 to 2 stop bits, all resolved at elaboration from generics.

Independent TX/RX FIFOs

▶ Parameterisable depth (power of two), decoupling software from the line rate.

Noise-immune receiver

▶ 3-sample majority vote at every bit centre, with independent framing and parity checks.

Sticky error flags

▶ FRAME_ERR, PARITY_ERR and OVERRUN, individually cleared via CTRL.ERR_CLR, alongside the maskable interrupt.

Self-clearing FIFO reset

▶ Either FIFO can be cleared from a CTRL strobe bit, with no need to touch the AXI reset.

Vendor-agnostic RTL

▶ No vendor primitives are instantiated; the same source builds unmodified on Xilinx, Altera, Lattice and Microchip.

Bare-metal C driver included

▶ Blocking, timeout and non-blocking byte/buffer transfers, plus error and FIFO control, no OS dependency beyond <stdint.h>.