IP Cores
High-performance hardware implementations for mission-critical applications.
I2C Master IP
The RunX I2C Master Controller IP resolves multi-master arbitration entirely in hardware, and can launch up to 255 back-to-back transactions from a single START request.
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SPI Master/Slave IP
The RUNX SPI Master/Slave IP is a core that houses an independent master and slave, and can run in Standard, 3-Wire, Dual and Quad modes selected at run time
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UART Controller IP
The RunX UART Controller IP has a noise-hardened receiver that samples every bit with a 3-sample majority vote, and is a fully configurable AXI4-Lite UART core data bits, parity and stop bits all set at elaboration
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